1. Field of the Invention
The present invention relates to clock technologies for reducing power consumption of semiconductor integrated circuits.
2. Description of the Prior Art
With operation speed of a semiconductor integrated circuit becoming faster in recent years, a percentage of clock-related power consumption in the total power consumed by a semiconductor integrated circuit has been becoming larger. With this being a background, an increased number of clock-related power reduction technologies have been disclosed.
The above-mentioned clock-related power reduction technologies can be broadly grouped into the following five categories:    1. a method for achieving a reduction in power consumption by stopping supplying clocks or by supplying very slow clocks to an unused and unnecessary portion of a circuit;    2. a method for achieving a reduction in power consumption with a specially devised clock or a specially devised clock receiving portion of the circuit consisting of a flip-flop, a latch circuit, or the like;    3. a method for achieving a reduction in power consumption by grouping circuit functions into a few modes and managing the power or the clock for each functional block in accordance with the mode thereof by using dedicated programmed instructions;    4. a method for achieving a reduction in power consumption by adding a change-clock instruction when programs are compiled so as to change the clock speed in accordance with circuit function; and    5. a method for achieving a reduction in power consumption by reducing the clock speed when an instruction requiring an access to a slower peripheral circuit is executed.
First, among the above-mentioned conventional technologies, method 1, “a method for achieving a reduction in power consumption by stopping supplying clocks or by supplying very slow clocks to an unused and unnecessary portion of a circuit,” is widely practiced and applied to a small to a large portion of a circuit in various levels. For example, the Japanese Patent Application Laid-Open No. H8-18008 discloses a technology relating to a semiconductor integrated circuit that makes a reduction in power consumption possible by preventing power from being wasted by unused functional blocks. Using this technology, the device controls supply of clock and stops supplying clock to the functional block that is unused at a certain stage. This technology, collectively called a gated circuit, is effective in reducing the power consumption to a large extent.
A similar technology is disclosed by the Japanese Patent Application Laid-Open No. H6-112810. In a digital integrated circuit device comprising a plurality of functional circuit blocks including a used first block and an unused second block in specific modes such as a stand-by mode, power is conserved by reducing current passing through the unused second block by stopping or slowing down the clock supplied thereto.
Another technology disclosed by the Japanese Patent Application Laid-Open No. H6-295243 proposes a data processing device having a pipeline in which a clock being supplied to some stages thereof that are waiting for another stage to complete a time-taking process executed therein, is suspended.
Next, among the above-mentioned conventional technologies, method 2, “a method for achieving a reduction in power consumption with a specially devised clock,” is shown in various forms. One example that represents this technology is a technology introduced in Section 2.1.7.1 “A Small-Amplitude Clock Technology” of a book entitled “Low-power High-speed LSI Circuits & Technology” edited by Takayasu Sakurai and published by Realize Company, in which methods for achieving a power reduction with a half-amplitude clock or a specially devised flip-flop circuit are introduced.
Regarding method 3, the Japanese Patent Application Laid-Open Nos. H5-210433 and H6-332583 disclose a power controller for digital electronic equipment, a processor with the power controller, and power management system for digital electronic equipment with the processor in which, for example, voltage or a clock speed is changed at any given time by using an instruction that is added to a set of executable programs so as to control a power supply or a clock frequency. To be more specific, in the above-mentioned device and system, instruction codes purposed for switching power on and off or changing the clock speed are arranged and executed for each internal functional block so as to regulate the power or clock being supplied thereto according to the function mode that the device or system is in. It is suggested that, in many cases, the circuit function be grouped into some modes such as a stand-by or operating mode and that the power or clock be regulated accordingly for a circuit that is barely performing operation.
Among the above-mentioned conventional technologies, method 4, “a method for achieving a reduction in power consumption by inserting a change-clock instruction when programs are compiled,” for example, is disclosed in the Japanese Patent Application Laid-Open No. H9-22318 as a technology relating to a processor and control method therefor. In this method, a unit cycle for which the clock is changed plays an important part. In other words, optimizing the process speed by controlling the clock speed in detail requires an insertion of the change-clock instruction too often, which eventually gives an adverse effect to the processing speed to a large degree. On the other hand, reducing the insertions of the change-clock instruction results in a rough control, which, in turn, reduces the processing speed unnecessarily because an overall speed is reduced by a slow circuit. If the processing speed has priority, then the clock can not be slowed down, thereby not contributing to reducing power.
Among the above-mentioned conventional technologies, method 5, “a method for achieving a reduction in power consumption by reducing the clock speed when an instruction requiring an access to a slow peripheral circuit is executed,” is, for example, disclosed by the Japanese Patent Application Laid-Open No. S62-232053 as a technology relating to an operation speed controlling device for microcomputer. In this case, even if the slow peripheral circuit is slow only in write time, the entire system must operate at that slow speed as long as the slow peripheral circuit is accessed, thereby slowing the entire system unnecessarily.
The Japanese Patent Application Laid-Open No. H8-147161, in light of the above-mentioned drawback, discloses a technology relating to a data processor that can minimize the reduction in processing speed by inserting a wait state only when a slow peripheral circuit is accessed for reading data. Although this technology is effective in reducing power while maintaining a reduction in processing speed at a minimum, the power consumption for every execution cycle varies to a large extent. In other words, even if power consumed during the wait state is small due to lighter internal operation, the peak current appearing in a cycle before the wait state tends to increase due to an increased number of jobs that are processed simultaneously.
As another method than the five conventional technologies as described before, the Japanese Patent Application Laid-Open No. H8-272479 discloses a variable clock generation device in which different clocks are respectively given to each individual functional unit according to function status thereof.
Described hereinafter with reference to FIGS. 11A and 11B are drawbacks of the conventional method 1, “a method for achieving a reduction in power consumption by stopping supplying clocks to an unused and unnecessary portion of a circuit.” FIG. 11A is a schematic diagram showing a general circuit configuration of a semiconductor integrated circuit and FIG. 11B is a table showing the status of each circuit block. A semiconductor integrated circuit 70 comprises: a block A 71, a block B 72, and a block C 73 each performing predetermined operation and processing; a clock generator 74; and a CPU 75 controlling each of the aforementioned circuits.
If one or more of the blocks operate in an instant during any given period of time, the semiconductor integrated circuit 70 must supply the same clock as used in an ordinary operation to the particular blocks that perform the operation. As a result, the semiconductor integrated circuit 70 contributes less to power saving even if the semiconductor integrated circuit 70 controls the other circuits in three modes consisting of supplying clock signal, stopping clock signal, and supplying a slower clock to each block. For example, as shown in FIG. 11B, the block A 71 operates very actively in Cycle 3 while the block C 73 operates barely noticeably during the same period. This means that an amount of saved power is equivalent to the power that is saved by the block B 72 that never operates during the same period.
Furthermore, semiconductor integrated circuits that have been developed recently, have a decreased number of functional blocks that can be halted entirely during wait mode such as stand-by mode. Because of this, the method for halting the clock entirely can not be applicable in many cases. To cope with this problem, a method to control the clock during stand-by mode slower than during operating mode has been disclosed. However this method does not teach any measures relating to the operating mode. This means that even in the case where even a slower clock is sufficient, an ordinary faster clock is kept being supplied, resulting in no reduction in power even during the wasteful operation.
Among the conventional technologies, as method 2, “a method for achieving a reduction in power consumption with a specially devised clock,” in which amplitude of the clock is reduced to half or the like is disclosed. This method requires additional wiring for power supply, different from the one used for clocking a logic circuit, and has such drawbacks as an increased chip size and a reduced circuit noise margin.
Among the conventional technologies, method 3, “a method for achieving a reduction in power consumption by grouping circuit functions into a few modes and managing the power or the clock for each functional block in accordance with the mode thereof by using dedicated programmed instructions,” requires that the circuit be divided clearly into a few modes. The Japanese Patent Application Laid-Open No. H9-22318 discloses the processor and control method therefor, in which instructions must be added into an existing set of programs after an analysis of effective ways for reducing power consumption.
In the conventional method 4, “a method for achieving a reduction in power consumption by inserting a change-clock instruction when programs are compiled so as to change the clock speed in accordance with the circuit function,” processing is halted when the change-clock instruction is executed. Additionally, as previously described, this method has a drawback in which a detailed control requires that the clock speed be changed frequently, resulting in accumulation of wasteful time.
In the conventional method 5, “a method for achieving a reduction in power consumption by reducing the clock speed when an instruction requiring an access to a slower peripheral circuit is executed,” a wait state is usually added when the system accesses a peripheral circuit, such as a memory circuit that operates at a speed slower than the system speed. During this period, circuits not relating to said access, maintain the status thereof without making any process. Even so, it is necessary to keep controlling these circuits with clocks for keeping the status thereof, resulting in a wasteful circuit operation. The Japanese Patent Application Laid-Open Nos. H3-55614, H2-118811, and S62-232053 disclose methods for slowing down the clock in accordance with the memory processing speed without adding a wait state as a technology for use in an electronic device, a microcomputer, and an operation speed controlling device for microcomputer. However, in these methods, memory access is achieved at considerable penalties in the operation speed of the system.
As another method than the five conventional technologies as described before, the Japanese Patent Application Laid-Open No. H8-272479 discloses a variable clock generation device. In this device, when multiple processes are simultaneous performed, each process requires a different time to be completed depending on the contents of the process. In many cases, a process that has been completed earlier maintains the resulting data thereof until a slower process is completed. Controlling with clocks is necessary for maintaining the data, resulting in a wasteful circuit operation.